% ThinkPad X200 

It is believed that all X200 laptops are compatible. X200S and X200
Tablet will also work, [depending on the configuration](#x200s).

It \*might\* be possible to put an X200 motherboard in an X201 chassis,
though this is currently untested by the libreboot project. The same may
also apply between X200S and X201S; again, this is untested. **It's
most likely true.**

There are two possible flash chip sizes for the X200: 4MiB (32Mbit) or
8MiB (64Mbit). This can be identified by the type of flash chip below
the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16.

**The X200 laptops come with the ME (and sometimes AMT in addition)
before flashing libreboot. Libreboot disables and removes it by using a
modified descriptor: see [gm45\_remove\_me.html](gm45_remove_me.html)**
(contains notes, plus instructions)

Flashing instructions can be found at
[../install/\#flashrom](../install/#flashrom)

EC update {#ecupdate}
=========

It is recommended that you update to the latest EC firmware version. The
[EC firmware](https://libreboot.org/faq/#firmware-ec) is separate from
libreboot, so we don't actually provide that, but if you still have
Lenovo BIOS then you can just run the Lenovo BIOS update utility, which
will update both the BIOS and EC version. See:

-   <https://libreboot.org/docs/install/index.html#flashrom>
-   <http://www.thinkwiki.org/wiki/BIOS_update_without_optical_disk>

NOTE: this can only be done when you are using Lenovo BIOS. How to
update the EC firmware while running libreboot is unknown. Libreboot
only replaces the BIOS firmware, not EC.

Updated EC firmware has several advantages e.g. bettery battery
handling.

Compatibility (without blobs) {#compatibility_noblobs}
-----------------------------

### Hardware virtualization (vt-x) {#hwvirt}

The X200, when run without CPU microcode updates in coreboot, currently
kernel panics if running QEMU with vt-x enabled on 2 cores for the
guest. With a single core enabled for the guest, the guest panics (but
the host is fine). Working around this in QEMU might be possible; if
not, software virtualization should work fine (it's just slower).

On GM45 hardware (with libreboot), make sure that the *kvm* and
*kvm\_intel* kernel modules are not loaded, when using QEMU.

The following errata datasheet from Intel might help with investigation:
<http://download.intel.com/design/mobile/specupdt/320121.pdf>

Anecdotal reports from at least 1 user suggests that some models with
CPU microcode 1067a (on the CPU itself) might work with vt-x in
libreboot.

X200S and X200 Tablet. {#x200s}
----------------------

X200S and X200 Tablet have raminit issues at the time of writing (GS45
chipset. X200 uses GM45).

X200S and X200 Tablet are known to work, but only with certain CPU+RAM
configurations. The current stumbling block is RCOMP and SFF, mentioned
in <https://www.cs.cmu.edu/~410/doc/minimal_boot.pdf>.

The issues mostly relate to raminit (memory initialization). With an
unpatched coreboot, you get the following:
[text/x200s/cblog00.txt](text/x200s/cblog00.txt). No SODIMM combination
that was tested would work. At first glance, it looks like GS45 (chipset
that X200S uses. X200 uses GM45) is unsupported, but there is a
workaround that can be used to make certain models of the X200S work,
depending on the RAM.

The datasheet for GS45 describes two modes: low-performance and
high-performance. Low performance uses the SU range of ultra-low voltage
procesors (SU9400, for example), and high-performance uses the SL range
of processors (SL9400, for example). According to datasheets, GS45
behaves very similarly to GM45 when operating in high-performance mode.

The theory then was that you could simply remove the checks in coreboot
and make it pass GS45 off as GM45; the idea is that, with a
high-performance mode CPU (SL9400, for example) it would just boot up
and work.

This suspicion was confirmed with the following log:
[text/x200s/cblog01.txt](text/x200s/cblog01.txt). The memory modules in
this case are 2x4GB. ~~**However, not all configurations work:
[text/x200s/cblog02.txt](text/x200s/cblog02.txt) (2x2GB) and
[text/x200s/cblog03.txt](text/x200s/cblog03.txt) (1x2GB) show a failed
bootup.**~~ *False alarm. The modules were mixed (non-matching). X200S
with high-performance mode CPU will work so long as you use matching
memory modules (doesn't matter what size).*

This was then pushed as a patch for coreboot, which can be found at
<http://review.coreboot.org/#/c/7786/> (libreboot merges this patch in
coreboot-libre now. Check the 'getcb' script in src or git).

### Proper GS45 raminit {#x200s_raminit}

A new northbridge gs45 should be added to coreboot, based on gm45, and a
new port x200st (X200S and X200T) should be added based on the x200
port.

This port would have proper raminit. Alternatively, gs45 (if raminit is
taken to be the only issue with it) can be part of gm45 northbridge
support (and X200S/Tablet being part of the X200 port) with conditional
checks in the raminit that make raminit work differently (as required)
for GS45. nico\_h and pgeorgi/patrickg in the coreboot IRC channel
should know more about raminit on gm45 and likely gs45.

pgeorgi recommends to run SerialICE on the factory BIOS (for X200S),
comparing it with X200 (factory BIOS) and X200 (gm45 raminit code in
coreboot), to see what the differences are. Then tweak raminit code
based on that.

Trouble undocking (button doesn't work)
----------------------------------------

This person seems to have a workaround:
<https://github.com/the-unconventional/libreboot-undock>

LCD compatibility list {#lcd_supported_list}
----------------------

LCD panel list (X200 panels listed there):
<http://www.thinkwiki.org/wiki/TFT_display>

All LCD panels for the X200, X200S and X200 Tablet are known to work.

### AFFS/IPS panels {#ips}

#### X200

Adapted from
<https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-X200>

Look at wikipedia for difference between TN and IPS panels. IPS have
much better colour/contrast than a regular TN, and will typically have
good viewing angles.

These seem to be from the X200 tablet. You need to find one without the
glass touchscreen protection on it (might be able to remove it, though).
It also must not have a digitizer on it (again, might be possible to
just simply remove the digitizer).

-   BOE-Hydis HV121WX4-120, HV121WX4-110 or HV121WX4-100 - cheap-ish,
    might be hard to find

-   Samsung LTN121AP02-001 - common to find, cheap

**If your X200 has an LED backlit panel in it, then you also need to get
an inverter and harness cable that is compatible with the CCFL panels.
To see which panel type you have, see
[\#led\_howtotell](#led_howtotell). If you need the inverter/cable, here
are part numbers: 44C9909 for CCFL LVDS cable with bluetooth and camera
connections, and 42W8009 or 42W8010 for the inverter.**

There are glossy and matte versions of these. Matte means anti-glare,
which is what you want (in this authors opinion).

Refer to the HMM (hardware maintenance manual) for how to replace the
screen.

Sources:

-   [ThinkPad Forums - Matte AFFS Panel on
    X200](http://forum.thinkpads.com/viewtopic.php?f=2&t=84941)
-   [ThinkPad Forums - Parts for X200 AFFS
    Mod](http://forum.thinkpads.com/viewtopic.php?p=660662#p660662)
-   [ThinkWiki.de - X200
    Displayumbau](http://thinkwiki.de/X200_Displayumbau)

### X200S

<http://forum.thinkpads.com/viewtopic.php?p=618928#p618928> explains
that the X200S screens/assemblies are thinner. You need to replace the
whole lid with one from a normal X200/X201.

How to tell if it has an LED or CCFL? {#led_howtotell}
-------------------------------------

Some X200s have a CCFL backlight and some have an LED backlight, in
their LCD panel. This also means that the inverters will vary, so you
must be careful if ever replacing either the panel and/or inverter. (a
CCFL inverter is high-voltage and will destroy an LED backlit panel).

CCFLs contain mercury. An X200 with a CCFL backlight will (****unless it
has been changed to an LED, with the correct inverter. Check with your
supplier!) the following: *"This product contains Lithium Ion Battery,
Lithium Battery and a lamp which contains mercury; dispose according to
local, state or federal laws"* (one with an LED backlit panel will say
something different).

Hardware register dumps {#regdumps}
-----------------------

The coreboot wiki
[shows](http://www.coreboot.org/Motherboard_Porting_Guide) how to
collect various logs useful in porting to new boards. Following are
outputs from the X200:

-   BIOS 3.15, EC 1.06
    -   [hwdumps/x200/](hwdumps/x200/)

RAM, S3 and microcode updates {#ram_s3_microcode}
=============================

Not all memory modules work. Most of the default ones do, but you have
to be careful when upgrading to 8GiB; some modules work, some don't.

Someone on reddit also did their own research on RAM compatibility: [on
this
post](https://www.reddit.com/r/libreboot/comments/5ax17e/liberated_x200_is_really_picky_with_memory/)

[This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might
be useful for RAM compatibility info (note: coreboot raminit is
different, so this page might be BS)

pehjota started collecting some steppings for different CPUs on several
X200 laptops. You can get the CPUID by running:\
\$ **dmesg | sed -n 's/\^.\* microcode: CPU0
sig=0x\\(\[\^,\]\*\\),.\*\$/\\1/p'**

What pehjota wrote: The laptops that have issues resuming from suspend,
as well as a laptop that (as I mentioned earlier in \#libreboot) won't
boot with any Samsung DIMMs, all have CPUID 0x10676 (stepping M0).

What pehjota wrote: Laptops with CPUID 0x167A (stepping R0) resume
properly every time and work with Samsung DIMMs. I'll need to do more
testing on more units to better confirm these trends, but it looks like
the M0 microcode is very buggy. That would also explain why I didn't
have issues with Samsung DIMMs with the Lenovo BIOS (which would have
microcode updates). I wonder if VT-x works on R0.

What pehjota wrote: As I said, 10676 is M0 and 1067A is R0; those are
the two CPUIDs and steppings for Intel Core 2 Duo P8xxx CPUs with
factory microcode. (1067 is the family and model, and 6 or A is the
stepping ID.)

**TODO: check the CPUIDs and test S3 resume and/or KVM on any C2D
systems (including non-P8xxx ones, which I don't have here) you have
available. I'd be curious if you could confirm these results.** It
might not be coreboot that's buggy with raminit/S3; it might just be
down to the microcode updates.

Unsorted notes {#unsorted}
--------------

    <sgsit> do you know if it's possible to flash thinkpads over the LPC debug connector at the front edge?
    <sgsit> that would make life much easier for systems like this
    <sgsit> all the Wistron manufactured systems have this thing called a "golden finger", normally at the front edge of the board
    <sgsit> you can plug a board in which gives diagnostic codes but i'm wondering whether it is capable of more
    <sgsit> http://www.endeer.cz/bios.tools/bios.html

Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\
Copyright © 2015 Patrick "P. J." McDermott <pj@pehjota.net>\
This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt)
% Flashing the X200 with a BeagleBone Black 

Initial flashing instructions for X200.

This guide is for those who want libreboot on their ThinkPad X200 while
they still have the original Lenovo BIOS present. This guide can also be
followed (adapted) if you brick your X200, to know how to recover.

-   [X200 laptops with libreboot pre-installed](#preinstall)
-   [Flash chips](#flashchips)
-   [MAC address](#macaddress)
-   [Initial BBB configuration and installation procedure](#clip)
-   [Boot it!](#boot)
-   [Wifi](#wifi)
-   [wwan](#wwan)
-   [Memory](#memory)
-   [X200S and X200 Tablet users: GPIO33 trick will not work.](#gpio33)

X200 laptops with libreboot pre-installed {#preinstall}
=========================================

If you don't want to install libreboot yourself, companies exist that
sell these laptops with libreboot pre-installed, along with a free
GNU+Linux distribution.

Check the [suppliers](../../suppliers) page for more information.

Flash chip size {#flashchips}
===============

Use this to find out:
    # flashrom -p internal -V

The X200S and X200 Tablet will use a WSON-8 flash chip, on the bottom of
the motherboard (this requires removal of the motherboard). **Not all
X200S/X200T are supported; see
[../hcl/x200.html\#x200s](../hcl/x200.html#x200s).**

MAC address {#macaddress}
===========

On the X200/X200S/X200T, the MAC address for the onboard gigabit
ethernet chipset is stored inside the flash chip, along with other
configuration data.

Keep a note of the MAC address before disassembly; this is very
important, because you will need to insert this into the libreboot ROM
image before flashing it. It will be written in one of these locations:

![](images/x200/disassembly/0002.jpg)
![](images/x200/disassembly/0001.jpg)

Initial BBB configuration {#clip}
=========================

Refer to [bbb\_setup.html](bbb_setup.html) for how to set up the BBB for
flashing.

The following shows how to connect the clip to the BBB (on the P9
header), for SOIC-16 (clip: Pomona 5252):

    POMONA 5252 (correlate with the BBB guide)
    ===  front (display) on your X200 ====
     NC              -       - 21
     1               -       - 17
     NC              -       - NC
     NC              -       - NC
     NC              -       - NC
     NC              -       - NC
     18              -       - 3.3V (PSU)
     22              -       - NC - this is pin 1 on the flash chip
    ===  back (palmrest) on your X200 ===
    This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack.
    Here is a photo of the SOIC-16 flash chip. Pins are labelled:

                

The following shows how to connect the clip to the BBB (on the P9
header), for SOIC-8 (clip: Pomona 5250):

    POMONA 5250 (correlate with the BBB guide)
    ===  left side of the X200 (where the VGA port is) ====
     18              -       - 1
     22              -       - NC
     NC              -       - 21
     3.3V (PSU)      -       - 17 - this is pin 1 on the flash chip. in front of it is the screen.
    ===  right side of the X200 (where the audio jacks are) ===
    This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack.
    Here is a photo of the SOIC-8 flash chip. The pins are labelled:

    Look at the pads in that photo, on the left and right. Those are for SOIC-16. Would it be possible to remove the SOIC-8 and solder a SOIC-16
    chip on those pins?

**On the X200S and X200 Tablet the flash chip is underneath the board,
in a WSON package. The pinout is very much the same as a SOIC-8, except
you need to solder (there are no clips available).\
The following image shows how this is done:**\
![](images/x200/wson_soldered.jpg "Copyright 2014 Steve Shenton <sgsit@libreboot.org> see license notice at the end of this document")\
In this image, a pin header was soldered onto the WSON. Another solution
might be to de-solder the WSON-8 chip and put a SOIC-8 there instead.
Check the list of SOIC-8 flash chips at
[../hcl/gm45\_remove\_me.html\#flashchips](../hcl/gm45_remove_me.html#flashchips)
but do note that these are only 4MiB (32Mb) chips. The only X200 SPI
chips with 8MiB capacity are SOIC-16. For 8MiB capacity in this case,
the X201 SOIC-8 flash chip (Macronix 25L6445E) might work.

The procedure
-------------

This section is for the X200. This does not apply to the X200S or X200
Tablet (for those systems, you have to remove the motherboard
completely, since the flash chip is on the other side of the board).

Remove these screws:\
![](images/x200/disassembly/0003.jpg)

Push the keyboard forward, gently, then lift it off and disconnect it
from the board:\
![](images/x200/disassembly/0004.jpg)
![](images/x200/disassembly/0005.jpg)

Pull the palm rest off, lifting from the left and right side at the back
of the palm rest:\
![](images/x200/disassembly/0006.jpg)

Lift back the tape that covers a part of the flash chip, and then
connect the clip:\
![](images/x200/disassembly/0007.jpg)
![](images/x200/disassembly/0008.jpg)

On pin 2 of the BBB, where you have the ground (GND), connect the ground
to your PSU:\
![](images/x200/disassembly/0009.jpg)
![](images/x200/disassembly/0010.jpg)

Connect the 3.3V supply from your PSU to the flash chip (via the clip):\
![](images/x200/disassembly/0011.jpg)
![](images/x200/disassembly/0012.jpg)

Of course, make sure that your PSU is also plugged in and turn on:\
![](images/x200/disassembly/0013.jpg)

This tutorial tells you to use an ATX PSU, for the 3.3V DC supply. The
PSU used when taking these photos is actually not an ATX PSU, but a PSU
that is designed specifically for providing 3.3V DC (an ATX PSU will
also work):\
![](images/x200/disassembly/0014.jpg)

Now, you should be ready to install libreboot.

Flashrom binaries for ARM (tested on a BBB) are distributed in
libreboot\_util. Alternatively, libreboot also distributes flashrom
source code which can be built.

Log in as root on your BBB, using the instructions in
[bbb\_setup.html\#bbb\_access](bbb_setup.html#bbb_access).

Test that flashrom works:
    # ./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512
In this case, the output was:

    flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l)
    flashrom is free software, get the source code at http://www.flashrom.org
    Calibrating delay loop... OK.
    Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi.
    Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi.
    Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi.
    Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E"
    Please specify which chip definition to use with the -c <chipname> option.

How to backup factory.rom (change the -c option as neeed, for your flash
chip):\
\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r
factory.rom**\
\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r
factory1.rom**\
\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r
factory2.rom**\
Note: the **-c** option is not required in libreboot's patched
flashrom, because the redundant flash chip definitions in *flashchips.c*
have been removed.\
Now compare the 3 images:

    # sha512sum factory\*.rom
If the hashes match, then just copy one of them (the factory.rom) to a
safe place (on a drive connected to another system, not the BBB). This
is useful for reverse engineering work, if there is a desirable
behaviour in the original firmware that could be replicated in coreboot
and libreboot.

Follow the instructions at
[../hcl/gm45\_remove\_me.html\#ich9gen](../hcl/gm45_remove_me.html#ich9gen)
to change the MAC address inside the libreboot ROM image, before
flashing it. Although there is a default MAC address inside the ROM
image, this is not what you want. **Make sure to always change the MAC
address to one that is correct for your system.**

Now flash it:\
\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -w
path/to/libreboot/rom/image.rom -V**

![](images/x200/disassembly/0015.jpg)

You might see errors, but if it says **Verifying flash\... VERIFIED** at
the end, then it's flashed and should boot. If you see errors, try
again (and again, and again); the message **Chip content is identical to
the requested image** is also an indication of a successful
installation.

Example output from running the command (see above):

    flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l)
    flashrom is free software, get the source code at http://www.flashrom.org
    Calibrating delay loop... OK.
    Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi.
    Reading old flash chip contents... done.
    Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716
    ERASE FAILED!
    Reading current flash chip contents... done. Looking for another erase function.
    Erase/write done.
    Verifying flash... VERIFIED.

Wifi
====

The X200 typically comes with an Intel wifi chipset, which does not work
without proprietary software. For a list of wifi chipsets that work
without proprietary software, see
[../hcl/\#recommended\_wifi](../hcl/#recommended_wifi).

Some X200 laptops come with an Atheros chipset, but this is 802.11g
only.

It is recommended that you install a new wifi chipset. This can only be
done after installing libreboot, because the original firmware has a
whitelist of approved chips, and it will refuse to boot if you use an
'unauthorized' wifi card.

The following photos show an Atheros AR5B95 being installed, to replace
the Intel chip that this X200 came with:\
![](images/x200/disassembly/0016.jpg)
![](images/x200/disassembly/0017.jpg)

WWAN
====

If you have a WWAN/3G card and/or sim card reader, remove them
permanently. The WWAN-3G card has proprietary firmware inside; the
technology is identical to what is used in mobile phones, so it can also
track your movements.

Not to be confused with wifi (wifi is fine).

Memory
======

You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs
(speed/size). Non-matching pairs won't work. You can also install a
single module (meaning, one of the slots will be empty) in slot 0.

NOTE: according to users repors, non matching pairs (e.g. 1+2 GiB) might
work in some cases.

Make sure that the RAM you buy is the 2Rx8 density.

In this photo, 8GiB of RAM (2x4GiB) is installed:\
![](images/x200/disassembly/0018.jpg)

Boot it! {#boot}
--------

You should see something like this:

![](images/x200/disassembly/0019.jpg)

Now [install GNU+Linux](../gnulinux/).

X200S and X200 Tablet users: GPIO33 trick will not work. {#gpio33}
--------------------------------------------------------

sgsit found out about a pin called GPIO33, which can be grounded to
disable the flashing protections by the descriptor and stop the ME from
starting (which itself interferes with flashing attempts). The theory
was proven correct; however, it is still useless in practise.

Look just above the 7 in TP37 (that's GPIO33):\
![](../hcl/images/x200/gpio33_location.jpg)

By default we would see this in lenovobios, when trying flashrom -p
internal -w rom.rom:

    FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only.
    FREG2: Warning: Management Engine region (0x00001000-0x005f5fff) is locked.

With GPIO33 grounded during boot, this disabled the flash protections as
set by descriptor, and stopped the ME from starting. The output changed
to:

    The Flash Descriptor Override Strap-Pin is set. Restrictions implied by
    the Master Section of the flash descriptor are NOT in effect. Please note
    that Protected Range (PR) restrictions still apply.

The part in bold is what got us. This was still observed:

    PR0: Warning: 0x007e0000-0x01ffffff is read-only.
    PR4: Warning: 0x005f8000-0x005fffff is locked.

It is actually possible to disable these protections. Lenovobios does,
when updating the BIOS (proprietary one). One possible way to go about
this would be to debug the BIOS update utility from Lenovo, to find out
how it's disabling these protections. Some more research is available
here:
<http://www.coreboot.org/Board:lenovo/x200/internal_flashing_research>

On a related note, libreboot has a utility that could help with
investigating this:
[../hcl/gm45\_remove\_me.html\#demefactory](../hcl/gm45_remove_me.html#demefactory)

Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\
This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt)
